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Low power and robust circuitry are permanent hotspots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence power dissipation in adiabatic logic and comparison of current mainstream clock generators suitable for adiabatic system. Based on the characteristics of current designs, using TSMC 180nm fabrication process, we propose a novel mixed clock generator, including four-phase source, switch controller and clock MUX to build a robust clock using only one reference clock. The test shows that below 600MHz, the proposed design has negligible signal attenuation with low power dissipation. We have also compared our work and current designs in device cost, and suitable work frequency based on circuit structure. Keywords—Adiabatic logic; slow charge; mixed clock generator